1. Field of the Invention
The present invention relates to a method of fabricating semiconductor transistors, and more particularly, to a method of utilizing selective epitaxial growth to fabricate strained-silicon transistors.
2. Description of the Prior Art
The selective epitaxial growth technology is widely applied in manufacturing numerous kinds of semiconductor devices, such as metal oxide semiconductor (MOS) transistors having raised source/drain regions and strained-silicon MOS transistors. The selective epitaxial growth technology is used to form an epitaxial layer on a single-crystalline substrate, in which the crystalline orientation of the epitaxial layer is almost identical to that of the substrate. Additionally, before the epitaxial layer is deposited on the substrate, a surface cleaning process must be performed to remove native oxides and other impurities from a surface of the substrate so that the epitaxial layer of a good quality can be obtained. Hence, the surface cleaning process plays an important role in the selective epitaxial growth technique.
Please refer to FIG. 1 through FIG. 3. FIG. 1 through FIG. 3 are perspective diagrams showing the means of fabricating strained-silicon transistors by utilizing a selective epitaxial growth according to the prior art. As shown in FIG. 1, a semiconductor substrate 10 is provided and a gate structure 12 is formed on the semiconductor substrate 10, in which the gate structure 12 includes a gate oxide layer 14, a gate 16 disposed on the gate oxide layer 14, a cap layer 18 disposed on the gate 16, and an oxide-nitride-oxide (ONO) offset spacer 20. Preferably, the gate oxide layer 14 is composed of silicon dioxide, the gate 16 is composed of doped polysilicon, and the cap layer 18 is composed of silicon nitride to protect the gate 16. Additionally, a shallow trench isolation (STI) 22 is formed around the active area of the gate structure 12 within the semiconductor substrate 10.
As shown in FIG. 2, an etching process, such as an anisotropic dry etching process is performed by utilizing the gate structure 12 as a mask to form two recesses 24 corresponding to the gate 16 in the semiconductor substrate 10, in which the depth of the recesses 24 is approximately 400 angstroms.
As shown in FIG. 3, after performing a wet cleaning step to the semiconductor substrate 10, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer 26 composed of silicon germanium (SiGe) within the recesses 24, in which the epitaxial layer 26 will be served as the source/drain region of the strained-silicon MOS transistor.
When the recesses 24 are etched, impurities such as carbon, fluoride, and hydrogen atoms will remain on the surface of the recesses 24 and ultimately influence the formation of the epitaxial layer later in the fabrication process. Hence, a cleaning step is often performed after the formation of the recesses 24 to utilize a sulfuric acid-hydrogen peroxide mixture (SPM) to remove the remaining particles from the surface of the recesses 24. Nevertheless, the conventional SPM is not entirely effective in cleaning off the remaining atoms from the surface of the recesses thereby resulting in defects and influencing the process of the selective epitaxial growth afterwards.